The main memory of a computer is usually formed from dynamic random access memory (DRAM) which provides memory cells that can be written up to 1015 times and from a practical perspective can be considered to allow an unlimited number of writes. Other memory technologies are now being investigated as an alternative to DRAM in order to scale to higher densities (thereby enabling smaller devices or more storage in the same physical space) or to provide non-volatile storage (therefore avoiding the need for periodic refresh and allowing the memory to retain its contents without continuing to be powered). A problem with many of these technologies, however, is that compared to DRAM they have a limited write endurance. Phase-change memory (PCM), which is an example of a new form of non-volatile memory (NVM), can endure 107-109 writes before it permanently fails and other technologies may have a significantly worse write endurance.
Programmers expect the failure-free properties of DRAM, irrespective of the memory technology used and consequently a number of techniques have been developed to mask memory failures from the software executing on the hardware. In an example, error correcting (or correction) codes (ECC) may be used where extra cells store redundant information which can be used to re-compute the original information in case of failure. Other examples include memory channel failover, where writes are issued to two or more channels and when failure occurs on a channel, it ceases to be used, and cell remapping where spare cells are used to replace faulty memory cells.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known memory management methods.